1) Field
Embodiments of the present invention generally relate to microelectronic fabrication, and more particularly to methods of patterning films.
2) Description of Related Art
Feature scaling in integrated circuits enables more capable electronic devices. Scaling to smaller features increases densities of functional units in a given form factor as well as increasing device processing speeds. Device scaling, however, is not without issue. For example, optimizing the performance of smaller devices becomes increasingly difficult. This is particularly true for the scaling of interconnect parasitics, which becomes performance limiting as the devices are scaled to the 32 nm technology node and beyond.
Parasitic capacitances have been traditionally reduced with the adoption of lower dielectric constant materials with successive generations of interconnect technology. Beginning with silicon dioxide having a dielectric constant of about 3.9, fluorine doped glasses were adopted, then various spin-on dielectrics, followed by carbon doped silicon glasses and finally, arriving at porous carbon doped silicon glass, the current state of the art in high volume manufacturing. However, even the most advanced porous, doped glass has a dielectric constant of at least 2.3 and interconnect parasitic capacitance is still performance limiting in many of today's circuit architectures and promises to be more so in tomorrow's architecture.
In response, the industry is increasingly looking at forming macroscale voids (those significantly larger than the voids in so-called porous films), also called air gaps, as a way to decrease line-to-line capacitance and cross-talk to enable scaling down to 32 nm and beyond. While air gaps within the interconnect layers have been experimented with for a number of years, they have yet to be adopted into mainstream interconnect technology. This is due to some methods suffering from reliability issues and others suffering from poor repeatability and yield issues, while still others are simply cost prohibitive.
One of the issues facing most any air gap interconnect technique is how to remove a sacrificial inter-metal dielectric (IMD) and form a sealed void. An implementation of the methods described herein may be employed for such a purpose.